4. ASYNC FIFO

In this assignment we will learn how to use an asynchronous FIFO.

This building block is very useful to exchange data between two clock domains, as signal sychronisation is provided.

Typically, ASYNC Fifos are used at communication boundaries, where an external interface is clocked differentely than the main logic.

4.1. Provided building block

In the previous assignment, we have learned the basics of a simple FIFO, and it’s implementation using a RAM memory for the target technology.

In this assignement, we will use an existing ASYNC Fifo implementation, because a reliable signal synchronisation can be hard to achieve.

The source code is available on the lecture repository:

You need to adapt and test the source code, the goal here is to figure out an existing design with little to no documentation available:

  • How do the input and outputs of the async_fifo seem to work?
  • Create a testbench similar to the FIFO testbench you wrote before, but with different clocks for reading and writing
    • Start by make a simple write to the fifo
    • After a while the empty signal should go away and the data out port should show the written data.
  • The FIFO won’t compile as is:
    • Search for the module instance representing a RAM memory.
    • Write a module of your own with the same name and input/outputs.
    • Fill this module with an instance of the technology RAM.
    • Connect the signals of the FIFO’s RAM memory to the technology RAM properly.