Lab¶
- 1. Assignment 1: Simple Counter
- 2. Assignment 2: Counter Synthesis
- 2.1. Tool Documentation System
- 2.2. Simple Synthesis
- 2.2.1. Preparing the synthesis run folder and script
- 2.2.2. Preparing the synthesis top level
- 2.2.3. Loading the Technology Library
- 2.2.4. Reading the Design
- 2.2.5. Performing Elaboration
- 2.2.6. Constraining the design
- 2.2.7. Creating Timing Groups
- 2.2.8. Performing synthesis
- 2.2.9. Quality and Timing report
- 2.2.10. Saving the output
- 2.3. Looking at the design using the GUI
- 2.4. Performance evaluation
- 2.5. Post Synthesis Simulation
- 2.6. Reset Type
- 2.7. Clock gating optimisation
- 3. Assignment 3: FIFO
- 4. ASYNC FIFO
- 5. System Place and route
- 5.1. System Overview
- 5.2. Simulation (optional)
- 5.3. Synthesis (optional)
- 5.4. Synthesis using ILIAS netlist
- 5.5. Place and Route -> Innovus
- 5.5.1. Start the tool
- 5.5.2. Cadence Help
- 5.5.3. Innovus Views
- 5.5.4. Load the design
- 5.5.5. Using the implement.tcl script
- 5.5.6. Floorplan
- 5.5.7. Input/Output Floorplaning (optional)
- 5.5.8. Power Planning
- 5.5.9. Placement
- 5.5.10. Clock Synthesis
- 5.5.11. Timing Debugger
- 5.5.12. Routing
- 5.5.13. Filling
- 5.5.14. Next steps if time allows:
- 6. Tools and Languages
- 6.1. MSYS2
- 6.2. Linux
- 6.3. Cadence Tools
- 6.4. Icarus Simulator
- 6.5. FSMDesigner
- 6.6. TCL
The lab is organised around a set of hardware blocks to describe in Verilog or VHDL, simulate and implement in the target technology: UMC65.
The basic Idea is first to design and verify a simple Counter, to which we will add some advanced features. A first technology synthesis will be performed to analyse the relationship between the RTL level and the Synthesised Gates.
In a second time, we will work on the First in First Out Building block (FIFO), which is an essential component of digital systems.
Finally, a System will be build out of the counter and FIFO components, by adding a communication input and output to the design, through which a user could externally configure the design’s internal features.

Rough overview of Lab System
Planned Assignments¶
Date | Work |
---|---|
27.04 | – |
04.05 | Assignment 1: Counter Simulation (Adder, Shift Register) |
11.05 | Assignment 1: Counter Simulation 2 |
18.05 | Assignment 2: Counter Synthesis |
25.05 | – (Feiertag) |
01.06 | Assignment 3: Fifo Using Register Memory (and optionally RAM) |
08.06 | Assignment 3: Fifo Using Register Memory (and optionally RAM) |
15.06 | – (Feiertag) |
22.06 | Assignment 4: ASYNC FIFO |
29.06 | Assignment 5: System Design: Communication Input/Output |
06.07 | Assignment 5: System Design: Communication Input/Output |
13.07 | Assignment 6: System Synthesis |
20.07 | Assignment 6: System Place and Route |
27.07 | Assignment 6: System Place and Route? |
Current State (SS17)¶
Date | Work |
---|---|
27.04 | – |
04.05 | Assignment 1: Counter Simulation (Adder, Shift Register) |
11.05 | Assignment 1: Counter Simulation 2 |
18.05 | Assignment 2: Counter Synthesis |
25.05 | – (Feiertag) |
01.06 | Assignment 3: Fifo Using Register Memory (and optionally RAM) |
08.06 | Assignment 3: Fifo Using Register Memory (and optionally RAM) |
15.06 | – (Feiertag) |
22.06 | Assignment 3: Fifo |
29.06 | Assignment 3/4: Fifo/ASYNC FIFO |
06.07 | Assignment 3/4: Fifo/ASYNC FIFO |
13.07 | Assignment 5: System Synthesis |
20.07 | Assignment 5: System Place and Route |
27.07 | Assignment 5: System Place and Route? |