6.4. Icarus Simulator¶
The Icarus Verilog Simulator is a simple open source Simulator for the verilog language.
Its feature set is rather limited, but it is sufficient to simulate simple designs, and is thus well suited to train yourself on your own PC.
6.4.1. Installation on Windows MSYS¶
First Install MSYS, and Add the extra package repositories.
Then install the iverilog package:
MINGW64 ~ $ pacman -Syy
MINGW64 ~ $ pacman -S mingw-w64-x86_64-iverilog mingw-w64-x86_64-libc++
6.4.2. Compiling the verilog code¶
Icarus Verilog works in two steps:
- First it compiles the Verilog into an executable file, just like a C Program.
- Run the Executable file
To compile the verilog code, you use the iverilog command, just as if you were using a C compiler like gcc:
To test this out, we will create a test folder:
MINGW64 ~ $ mkdir icarus-test
MINGW64 ~ $ cd icarus-test
MINGW64 ~/icarus-test $
Now, create a file using a text editor like nano, and add some Simulator Code like following:
File: test_testbench.v
module test_testbench; initial begin $display("Hello!"); end endmodule
To compile, simply run iverilog:
MINGW64 ~/icarus-test $ iverilog -o test_testbench test_testbench.v
The “-o test_testbench” option instructs icarus to create the executable form of the design under the file named “test_testbench”.
6.4.3. Running the Executable Format¶
To run the compiled design, use the vvp command:
MINGW64 ~/icarus-test $ vvp test_testbench
Hello!
MINGW64 ~/icarus-test $
As in this example, you should see the “Hello!” line, which corresponds to the “$display” function call in the testbench
6.4.4. Recompile and Rerun¶
Just repeat this compile and run steps when you change the design
6.4.5. Saving Simulation output¶
Icarus does not have an intergrated Graphical Interface, so you will have to use the verilog function to save a waveform to a file.
Here is how to add the required functions to your test bench. An example is also provided on Icarus Wiki Here <http://iverilog.wikia.com/wiki/GTKWAVE>
6.4.5.1. Activating the Waveform Dump¶
First you will have to activate Waveform saving to a File. We can use the previous example and add a register to be used as a clock:
File: test_testbench.v
module test_testbench; reg clock; initial begin $display("Hello!"); // Save to file test.vcd $dumpfile("test.vcd"); end endmodule
6.4.5.2. Selecting data to save¶
The Dump file won’t save all the values possible per default. The user has to select which signals to save using the $dumpvars command:
- If you use $dumpvars alone, it will start saving all the signal values in the design.
- If you want to select the data precisely you also can.
Look at this tutorial tutorial to learn how.
If we improve the example and add a clock generator:
File: test_testbench.v
module test_testbench; reg clk; always begin #5 clk <= ~clk; end initial begin clk = 0 ; $display("Hello!"); // Save to file test.vcd $dumpfile("test.vcd"); $dumpvars; // Stop after a while #1000 $finish(); end endmodule
Now run:
MINGW64 ~/icarus-test $ iverilog -o test_testbench test_testbench.v && vvp test_testbench
You should find a file called “test.vdc”
6.4.5.3. Open the Waveform using GTK Wave¶
You can install GTKWave in MSYS2 :
MINGW64 ~/icarus-test $ pacman -S mingw64/mingw-w64-x86_64-gtkwave
Then open the Waveform file:
MINGW64 ~/icarus-test $ gtkwave.exe test.vcd
The window opens, you can select on the left the “test_testbench” hierarchy, then on the bottom left the “clk” signal and drag it on the right. You can zoom out the waveform area using “CTRL+Mouse Wheel”, and you should see something like this:

6.4.5.4. Reload the waveform after a change¶
You can start GTK Wave in a separate command line, then resimulate your design, then in GTK Wave use the following menu:
File -> Reload Waveform
The window should update with the new data.