Lab

The lab is organised around a set of hardware blocks to describe in Verilog or VHDL, simulate and implement in the target technology: UMC65.

The basic Idea is first to design and verify a simple Counter, to which we will add some advanced features. A first technology synthesis will be performed to analyse the relationship between the RTL level and the Synthesised Gates.

In a second time, we will work on the First in First Out Building block (FIFO), which is an essential component of digital systems.

Finally, a System will be build out of the counter and FIFO components, by adding a communication input and output to the design, through which a user could externally configure the design’s internal features.

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Rough overview of Lab System

Planned Assignments

Date Work
27.04
04.05 Assignment 1: Counter Simulation (Adder, Shift Register)
11.05 Assignment 1: Counter Simulation 2
18.05 Assignment 2: Counter Synthesis
25.05 – (Feiertag)
01.06 Assignment 3: Fifo Using Register Memory (and optionally RAM)
08.06 Assignment 3: Fifo Using Register Memory (and optionally RAM)
15.06 – (Feiertag)
22.06 Assignment 4: ASYNC FIFO
29.06 Assignment 5: System Design: Communication Input/Output
06.07 Assignment 5: System Design: Communication Input/Output
13.07 Assignment 6: System Synthesis
20.07 Assignment 6: System Place and Route
27.07 Assignment 6: System Place and Route?

Current State (SS17)

Date Work
27.04
04.05 Assignment 1: Counter Simulation (Adder, Shift Register)
11.05 Assignment 1: Counter Simulation 2
18.05 Assignment 2: Counter Synthesis
25.05 – (Feiertag)
01.06 Assignment 3: Fifo Using Register Memory (and optionally RAM)
08.06 Assignment 3: Fifo Using Register Memory (and optionally RAM)
15.06 – (Feiertag)
22.06 Assignment 3: Fifo
29.06 Assignment 3/4: Fifo/ASYNC FIFO
06.07 Assignment 3/4: Fifo/ASYNC FIFO
13.07 Assignment 5: System Synthesis
20.07 Assignment 5: System Place and Route
27.07 Assignment 5: System Place and Route?