Design Digitaler Schaltkreise

  • Lecture
    • Introduction to DDS
    • Digital Design Flow Introduction
      • Global Definition of a System
      • Synchronous Logic Systems and Pipelining
      • System Specification
      • Verification
      • Technology Mapping
    • Verilog Hardware Description Language
      • Standard Programming languages and HDL
      • Register Transfer Level (RTL)
      • Synthesisable and Simulation Subsets
      • Hierarchy Definition
      • Signals: Input / Output
      • Pipeline Stage Definition
      • Parameterizing a Module
      • Value Assignment Syntaxes
      • Simulation Testbench
    • Advanced Design Methods
      • Clock Domain Crossing
      • State Machines
      • Demonstrator
      • Simulator Integration using VPI
      • Extra: Parsing Library file
      • Advanced Simulation
    • Gate Level Synthesis
      • Lecture Slides
      • The synthesis Flow
      • Resources
      • Static Timing Analysis
      • Standard Cells
      • Design Constraints
      • Synthesis Output
      • Advanced Topics
    • Place and route
      • Part 1 - Lecture Slides
      • Part 2 - Lecture Slides
  • Lab
    • 1. Assignment 1: Simple Counter
      • 1.1. Cadence Tools
      • 1.2. Organising your work Folder
      • 1.3. Assignments Plan
      • 1.4. First Version
      • 1.5. Simulation Improvement and Next feature
      • 1.6. Making Configurable
      • 1.7. Shift Register output
      • 1.8. Short Conclusion
    • 2. Assignment 2: Counter Synthesis
      • 2.1. Tool Documentation System
      • 2.2. Simple Synthesis
      • 2.3. Looking at the design using the GUI
      • 2.4. Performance evaluation
      • 2.5. Post Synthesis Simulation
      • 2.6. Reset Type
      • 2.7. Clock gating optimisation
    • 3. Assignment 3: FIFO
      • 3.1. Work Folder
      • 3.2. Register Memory FIFO
      • 3.3. RAM Memory FIFO
    • 4. ASYNC FIFO
      • 4.1. Provided building block
    • 5. System Place and route
      • 5.1. System Overview
      • 5.2. Simulation (optional)
      • 5.3. Synthesis (optional)
      • 5.4. Synthesis using ILIAS netlist
      • 5.5. Place and Route -> Innovus
    • 6. Tools and Languages
      • 6.1. MSYS2
      • 6.2. Linux
      • 6.3. Cadence Tools
      • 6.4. Icarus Simulator
      • 6.5. FSMDesigner
      • 6.6. TCL
    • Planned Assignments
    • Current State (SS17)
  • Sources and Online Access
    • ILIAS
    • Online Access
    • Offline Access
    • Sources Access
  • Glossary
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