5. System Place and route

5.1. System Overview

For this last assigment, a little design system was prepared. It is not really fully functional since no big assignment is planned around it but you will find a few circuit examples which have not been presented previously:

  • Clock Divider using a shift register
  • Serial Data receiving and transmitting using shift registers
  • Usage of the ASYNC Fifo as an interface between a fast Input/Output clock domain and a slower main logic clock domain.
  • Top level system containing Input/Output Cells from the technology library.
../../_images/system.png

Place and Route System Overview

The Design is availabe on the GIT repository, along with the scripts. You can run the tools yourself if you whish or used a pre-synthesised file you will find on ILIAS.

Repository path:

In the repository, you will find:

  • Verilog+Testbench sources
  • Synthesis+Constraints under the synthesis folder
  • State machine project for graphical tool (FSMDesigner)
  • Place and route scripts under “encounter”
  • A Makefile with targets showing how to run the various tools for this design

5.2. Simulation (optional)

If you have time, you can use the sources to run a simulation and modify the system if you want.

You can look for the clock divider and follow the datain/dataout signals to see how data is received and send.

5.3. Synthesis (optional)

The synthesis results can be found in ILIAS. If you want to run the synthesis by yourself, you have two options:

  • Get the source code and write the synthesis script yourself using the script from the sources as a reference
  • Run the synthesis from the source folder using the command::
    $ make -B synthesis
  • Don’t forget to load the tools in the terminal before starting

5.4. Synthesis using ILIAS netlist

If you are using the presynthesised design from ILIAS, place the netlist file in the folder: minisystem/synthesis/run/netlist/minisystem_top.gtl.v

5.5. Place and Route -> Innovus

The place and route tool is called Innovus. It’s usage require more detailed command calls than for synthesis, that’s why the source folder provides ready-to-use scripts which you should try to understand and reproduce for the most important parts. Most command usage require a lot of reading of the tools’s documentation so you can use the reference script.

In the encounter/ folder, you will find two scripts:

  • load_design.tcl just sets up the tool by loading the synthesized netlist and setting up the timing libraries
  • implement.tcl contains all the commands from floorplan setup to routing and result streamout.

5.5.1. Start the tool

Go in the minisystem folder and run:

minisystem $ make innovus

You can also go to the encounter folder, create a folder called run, enter it and start the tool:

minisystem $ cd encounter

minisystem/encounter$ mkdir run

minisystem/encounter/run $ cd run

minisystem $ innovus -win

Just like genus, innovus offers a command line, and a GUI window should start where you can see the physical design and manipulate it.

5.5.2. Cadence Help

Don’t forget to open and use the cadence help (see synthesis assigment) to look for precise informations on the commands.

5.5.3. Innovus Views

Innovus has three display views for the ASIC area:

  • The first two will show the unplaced objects so you can manipulate them
  • The last one is the physical view which shows all the structures (cells, wires etc…).

To change the views, using the toolbar on the top right of the window:

../../_images/innovus-views.png

Todo

Please note the name of the three views, you will be asked to switch between them later.

5.5.4. Load the design

As a first step, you can use the load_design.tcl script to setup innovus:

innovus:> source ../load_design.tcl

This steps takes a while.

Look at the load_design.tcl script and find out:

  • The Loaded technology libraries:
    • Which external components were loaded
  • The timing setup
    • Which timing libraries where used
    • Can you find which libraries are set for setup and hold analysis?
    • IS the setup correct?

5.5.5. Using the implement.tcl script

The implement.tcl script contains all the steps.

When going through the instructions, you should extract the relevant commands, save them to a separated script and run this script

5.5.6. Floorplan

The first step in the implementation script is floorplaning.

Here we can define the area available to place and route the circuit, and pre-place “hard macros”, i.e the RAM blocks:

The floorplan is made of two areas:

  • The core for the logic cells
  • The IO rows around the core for the Input/Output cells

Todo

Look in the implement script, how big is the core/area? Why?

Todo

Look in /var/autofs/cadence/umc-65/65nm-pads/ , search for the documentation PDF and find out how the IO row size was determined.

Now write the commands up to the “floorplan” command in script of your own, you can call it “floorplan.tcl”, and save it alongside the implement.tcl. Run it:

innovus:> source ../floorplan.tcl

Open the Innovus GUI window, type on the letter “f” to fit the view, the central area should have changed.

Now open the floorplan Innovus view, the are still looks empty because nothing was placed. On the bottom right of the design, there should be two grey boxes:

../../_images/fp-ram.png
  • These are the two RAM blocks from the FIFOs
  • Enable the Move menu from the top toolbar (play around to find the button)
  • Click on the RAM blocks to move them, and place them in the middle of the area.

Now open a new terminal and go to the encounter/run folder, there should be a file called “innovus.cmdx” where “x” increments everytime you open the tool. Open the latest “.cmd” file, and look at the bottom, you should see somme commands reproducing the GUI manipulation to place the RAMS:

  • Add the commands necessary to place the rams to the floorplan.tcl script.
  • Load the design again to clean Innovus by sourcing the load_design.tcl script again.
  • Source your improved floorplan.tcl script
  • Do the floorplan look ok?

Now run the commands untils the “Save DEF” point to finalize the floorplaning:

  • You should see some blue vertical lines on the GUI, they are made of the well tap cells spread on the are
  • You can look in the Standard Cell documentation (/var/autofs/cadence/umc-65/xxxxx/databook.pdf, see Synthesis assignments) for their description.
  • Zoom on the RAM block edges: Can you see the cell rows are cut to avoid cells being placed over the RAM blocks?
../../_images/fp-cutrow.png

Cutted row and Well taps

5.5.7. Input/Output Floorplaning (optional)

Around the core area, you will see the very few IO cells required for the system input and outputs.

These are placed by default and are not sufficient, since we also need to add for example power cells so the ASIC has pins to connect VDD and GND.

IO Cell usage is description in the databook/application note under: /var/autofs/cadence/umc-65/65nm-pads/doc/ :

  • Read the documentation and find out which cells are required to be added to the IO row for it to be complete
    • We are using only one digital power domain called (VDD_CORE and GND_CORE for power and ground)
  • Open the cadence help and in the Innovus Command Reference, search for the commands to:
    • Create a new IO cell
    • Place it
    • Delete created cells of a certain type (useful to develop a script placing cells correctely)
  • Write a little script that places some power and ground cells around the core along the normal Signal cells.
    • This step can take a while

5.5.8. Power Planning

Power planning can be done now, since the next steps will be automated, manually placed structures should be prepared before clock and routing are performed. Placement can also be done before power planning in case some cells require special connections which can only be done after placement.

You can save the Power Planning section of implement.tcl to a new script (power.tcl), and run it.

Go back to the GUI and open the physical view:

  • You should see power stripe, you now have to zoom in a lot to see between them
  • Some VIA connections should have been made between the striped and down to the RAMs too
../../_images/power-vias.png

5.5.9. Placement

The next step in the script is placement, which performs two operations:

  • Place Spare logic blocks. This could have been done earlier too
  • call “placeDesign” which places the standard cells

Run the Spare logic placement first, you should be able to find little “islands” of logic everywhere on the area

Then run placeDesign and checkPlace and wait:

  • The last run command is checking placement, make sure no violations are reported:
    • What are the checks run and reported?
  • Open the Physical View
  • On the Right side of the GUI, you can change the displayed layer and configuration
  • Try to modify the displayed layers to clearly the cells
../../_images/stdcells.png

Standard cells around the RAMS

5.5.10. Clock Synthesis

Clock synthesis is automated and requires little configuration for simple designs.

Look at the implement.tcl part about clock synthesis, see that the list of allowed Clock buffers is manually specified to prevent usage of big buffers which usually are not very efficient.

At the end of the process, a design optimisation using “optDesign” is performed for hold fixes:

  • Under report/timing you can find timing reports
  • Look for the reports before optDesign and after (look at the report names and the script to find which is which).
  • Are there any issue or changes?
    • If no issues are present, maybe the tool fixed the hold timing earlier
    • Compare with the placement hold timing report, there you should see a little change
  • Look for the clock synthesis reports and find the Global/Local Skew information

5.5.11. Timing Debugger

  • Use the GUI Menu Timing..Debug Timing to open a timing debugger
  • The setup timing has negative paths so you have paths to analyze
  • Once the debugger is openend, double-click a path on the botton to open the path analyzer
  • Look in the offered tabs to highlight the path on the GUI view, and look for the path interprepation
  • What would you do to help improve the path based on the timing interpretation help?
  • If you have time, you can modify the floorplaning and re-run the steps to improve the paths
    • Usually you can leave out some steps like power planning to test timing improvements and re-run fully later
../../_images/timing-debug.png

Timing debugger path list

../../_images/timingpath.png

Timing Path Analysis

5.5.12. Routing

Just like Design Clocking, the router works in a standalone manner.

For complex design, one has to use the documentation of the tool to see which router option should be enabled/disabled:

  • Which routing layer are enabled in our case, and why?
  • Run the routing steps from a separated script, then look at the GUI and zoom in the standard cells to find the routes
  • Look at the timing reports or debugger, note the evolution of timing

5.5.13. Filling

The last step in the script is adding fillers.

Fillers are not metal fillers, but cells which are placed in free area on the core:

  • Look back at the Standard Cell design description in the lecture, why do you think fillers are needed?
  • Run the filling step, and compare the core area with the routing results.

5.5.14. Next steps if time allows:

  • DRC/LVS in Virtuoso?
  • Constraints reloading to remove uncertainty