Gate Level Synthesis

Lecture Slides

Here are the lecture slides from the previous semester:

Download Here

Introduction

After studying the formal description of a logic circuit using a Hardware Description Language, we can look at how this description will be mapped to a real harware circuit.

A few concepts, which have a direct impact on how the logic will, have already been introduced and practised, like:

  • Defining Clock Synchronous logic blocks
  • Defining pipeline stages by using “non blocking” value updates
  • Defining a reset to bring a circuit into an initial state

As we have mentionned in the introduction to this lecture, we are following a so called “Semi-Custom” design flow.

This means that the circuit implementation is automated, based on a provided set of ready to use logic functions. The algorithms then only translate the HDL description to a logic network whose single functions are available a physical components to be used in the final circuit.

In this lecture part, we will try to detail all the required elements needed to build a final design, and also the required concept needed to make sure the circuit will be functional.

Resources

The resources are all the functional blocks which are not described using the behavorial model, but required for a physical implementation to be viable.

Some of the most common resources are going to be:

  • Memories like SRAM
  • Phased Locked Loop for clock multiplication and division.
  • Intellectual Property blocks (IP Block) : Any kind of design part which can be bought in from a third party provider

Design Data Preparation

We have presented various concepts needed to perform synthesis:

  • Ready to use logic library in the form of standard cells
  • Resources as external blocks
  • Timing specification